1. Field of the Invention
The present invention relates to a process used for fabricating metal oxide semiconductor field effect transistors, (MOSFET), devices, and more specifically to a process that allows different operating voltage devices to be obtained, while using only one gate oxide thickness.
2. Description of Prior Art
The ability to build faster and less costly complimentary metal oxide semiconductor, (CMOS), devices, is directly related to the ability of the semiconductor industry to achieve device micro-miniaturization. Smaller chip features result in a greater amount of chips per wafer, thus reducing the cost of CMOS chips. Device micro-miniaturization has been accomplished basically by the advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching, (RIE). Advances in terms of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, have allowed sub-micron images to be routinely obtained in photoresist layers. Also rapid development of dry etching, using anisotropic processes, have in turn allowed the sub-micron images in photoresist to be successfully transferred to underlying semiconductor materials.
Another trend in the semiconductor industry has been to build higher performing CMOS devices. Efforts have been made to reduce the channel length of CMOS devices. The ability to reduce channel lengths, or source to drain spacing, depend on the ability to reduce the image size of the polysilicon gate, which is used as a mask for the self aligned source and drain processs. Therefore the advances in photolithogaraphy and RIE disciplines also contribute to increases in device performance, as well as the previously mentioned cost benefits. Performance increases have also been realized from incremental reductions in capacitances. Gate insulators, composed of silicon dioxide, in the range of less then 100 Angstroms have been routinely used. The use of thin gate oxides can sometimes restrict the use of specific voltages, that may be large enough to create gate dielectric wearout or breakdown problems. Therefore to obtain the high performance with the use thin gate oxides, for specific CMOS chip locations, while insuring against wearout phenomena in other CMOS locations, where higher voltages are needed, engineers designed CMOS processes that satisfied both demands. This has been accomplished by creating thicker gate oxides, for areas using higher gate voltages, and using the thinner insulator, in regions demanding performance. However the ability to fabricate different gate insulator thicknesses on the same CMOS chip, can be costly and can also result in overall yield loss due to contamination phenomena. The simplest method for producing two thicknesses of gate insulator is: grow a gate oxide to a specific thickness; mask via photoresist techniques; etch away the first oxide from areas needing the other gate thickness; remove the masking photoresist; carefully clean the substrate; and grow the other thickness of gate oxide. This process is costly due to the increased process steps, as well as possilbly yield limited, due to the organic processing used between gate oxidations.
Another method, will now be described in this inventions, that will allow CMOS structures to perform at different operating voltages, while using only one gate oxide thickness. The method used will be to fabricate polysilicon gate electrodes, one doped in a conventional manner, while the gate supporting the higher voltage demands will be created using an intrinsic polysilicon gate interface. In U.S. Pat. No. 4,849,968, Gardiner, etal, described a polysilicon gate that was created via chemical vapor deposition of polysilicon which included a graded, insitu phosphorous doping procedure. The inventors started with an intrinsic layer of polysilicon and gradually increased the phosphorous introduction as the deposition proceeded. This was done primarily to avoid large grain growth of polysilicon, at the gate oxide interface, during subsequent high temperature procedures. The growth of the grains increased with increasing phosphorous concentration, and thus by initially limiting the amount of phosphorous doping, at the polysilicon-gate oxide interface, the polysilicon grain growth was limited. In this invention depleted gate CMOS devices, will be fabricated, using a doped polysilicon gate for the low operating voltage device, while a undoped, or partially doped polysilicon gate will be used for the device requiring higher operating voltages.